1. Field of the Invention
The present invention relates to multiplexer circuits and demultiplexer circuits. More particularly, the present invention relates to a multiplexer circuit for converting M parallel data signals of a bit into a serial data signal of M bits in synchronization with a clock signal, and a demultiplexer circuit for converting a serial data signal of M bits into M parallel data signals of a bit in synchronization with a clock signal.
2. Description of the Prior Art
FIG. 14 is a block diagram showing a structure of a conventional shift register type 4:1 multiplexer circuit 100 described in pp. 35-38 in "Bipolar Circuits and Technology Meeting", IEEE 1991. FIG. 15 is a timing chart showing the operation thereof. Referring to FIG. 14, multiplexer circuit 100 includes a clock signal input terminal C', data signal input terminals D0'-D3' and a data signal output terminal Q'. A clock signal C0 is applied to clock signal input terminal C'. As shown in FIG. 15(c), clock signal C0 attains a low level or a high level for every half cycle Tc/2. 4 parallel data signals I0-I3 of 4 bits are applied to data signal input terminals D0'-D3', respectively. As shown in (a) and (b) in FIG. 15, data signals I0-I3 attain a high level or a low level at 4 times the cycle of clock signal C0 in synchronization with a fall of clock signal C0.
Multiplexer circuit 100 includes flipflop circuits 102-104, 106-109, selector circuits 110-112, and a 3-input NOR gate 105.
Each element will be described hereinafter with reference to the circuit diagram of FIG. 16 and the timing chart of FIG. 17. Referring to FIG. 16, flipflop circuit 102 includes a clock signal input terminal C, a data signal input terminal D, data signal output terminals Q, QB, first and second reference potential terminals VB1, VB2, and first and second power supply terminals Vcc, Vee.
A clock signal C0 is applied to clock signal input terminal C. As show in FIG. 17(b), clock signal C0 attains a high level or a low level for every half cycle Tc/2. A data signal I is applied to data signal input terminal D. As shown in FIG. 17(a), data signal I attains a high level or a low level at the same synchronization of clock signal C2 in synchronization with a fall of clock signal C0.
A threshold potential of a logic amplitude of data signal I input to data signal input terminal D is applied to first reference potential terminal VB1. A threshold potential of a logic amplitude of clock signal C0 input to clock signal input terminal C is applied to second reference potential terminal VB2. A first power supply potential is applied to first power supply terminal Vcc. A second power supply potential lower than the first power supply potential is applied to second power supply terminal Vee.
Flipflop circuit 102 includes a master circuit and a slave circuit. The master circuit includes resistors R4, R5, bipolar transistors Q31-Q38, and constant current sources CS1214 CS14. Transistors Q31 and Q32 have their bases connected data signal input terminal D and first reference potential terminal VB1, and their collectors connected to first power supply terminal Vcc via resistors R4 and R5, respectively, and the commonly-connected emitters connected to the collector of transistor Q33. Transistors Q34 and Q35 have their bases connected to the collectors of transistors Q32 and Q31, respectively, their collectors connected to the collectors of transistors Q31 and Q32, respectively, and their commonly-connected emitters connected to the collector of transistor Q36. Transistors Q33 and Q36 have their bases connected to clock signal input terminal C and second reference potential terminal VB2, respectively, and their commonly-connected emitters connected to second power supply terminal Vee via constant current source CS12. Transistors Q37 and Q38 have their bases connected to the collectors of transistors Q32 and Q31, respectively, the collectors both connected to first power supply terminal Vcc, and their emitters connected to second power supply terminal Vee via constant current sources CS13 and CS14, respectively.
The slave circuit includes resistors R6, R7, bipolar transistors Q39-Q46, and constant current sources CS15-CS17. Transistors Q39 and Q40 have their bases connected to the emitters of transistors Q37 and Q38, respectively, the collectors connected to first power supply terminal Vcc via resistors R6 and R7, respectively, and the commonly-connected emitters connected to the collector of transistor Q41. Transistors Q42 and Q43 have their bases connected to the collectors of transistors Q40 and Q39, respectively, the collectors connected to the collectors of transistors Q40 and Q39, respectively, and the commonly-connected emitters connected to the collector of transistor Q44. Transistors Q41 and Q44 have their bases connected to second reference potential terminal VB2 and clock signal input terminal C, respectively, and the commonly-connected emitters connected to second power supply terminal Vee via constant current source CS15. Transistors Q45 and Q46 have their bases connected to the collectors of transistors Q40 and Q39, respectively, their collectors both connected to first power supply potential Vcc, and their emitters connected to data signal output terminals Q and QB, respectively, as well as to second power supply terminal Vee via constant current sources CS16 and CS17.
Bipolar transistors Q31 and Q32 and bipolar transistors Q39 and Q40 each form a data writing circuit, and bipolar transistors Q34 and Q35 and bipolar transistors Q42 and Q43 each form a data holding circuit.
The operation of flipflop circuit 102 of FIG. 16 will be described hereinafter. When clock signal C0 applied to data signal input terminal C attains a high level, bipolar transistors Q33 and Q44 are turned on, and the data writing circuit of the master circuit and the data holding circuit of the slave circuit are turned on. Transistors Q36 and Q41 are turned off, and the data holding circuit of the master circuit and the data writing circuit of the slave circuit are turned off. If the data signal (assumed to be ID1) applied to transistor Q31 attains a high level, transistor Q31 is turned on and transistor Q32 is turned off, whereby the current set by constant current source CS12 flows to resistor R4 via transistors Q31 and Q33. The voltage drop of resistor R4 causes reduction in the base potential of transistor Q38, whereby transistor Q38 is turned off to output a signal of a low level. Current does not flow to resistor R5 since transistor Q32 is turned off. Therefore, transistor Q37 is turned on to output a signal of a high level. Thus, data writing is effected in the master circuit. In the slave circuit, the data holding circuit is turned on, so that the previous data signal (assumed to be ID0) is held. This previous data is output via transistors Q45 and Q46. Transistors Q45 and Q46 provide complementary signals, as in the case of transistors Q37 and Q38.
When clock signal C0 applied to clock signal input terminal C is brought to a low level from a high level (time t2 in FIG. 17), bipolar transistors Q36 and Q41 are turned off, whereby the data holding circuit of the master circuit and the data writing circuit of the slave circuit are turned on. Transistors Q33 and Q44 are turned off, and the data writing circuit of the master circuit and the data holding circuit of the slave circuit are turned off. Bipolar transistors Q34 and Q35 have their base terminals and collector terminals cross-coupled. Therefore, transistor Q34 is turned on and transistor Q35 is turned off by data signal ID1 applied during a high level of clock signal C0. As a result, data signal ID1 is maintained. Transistors Q37 and Q38 continue to provide the same value to the slave circuit when clock signal C0 attains a high level.
The data writing circuit of the slave circuit is turned on, and transistors Q37 and Q38 provide signals of a high level and a low level, respectively. Therefore, transistor Q39 is turned on and transistor Q40 is turned off. As a result, the current set by constant current source CS15 flows through resistor R6 via transistors Q39 and Q41. This causes transistor Q46 to provide a signal of a low level. Because transistor Q40 is off, no current flows in resistor R7, and transistor Q45 provides a signal of a high level. Thus, data is updated in the slave circuit. A similar operation is carried out when the input data of data signal input terminal D attains a low level. In this case, transistor Q46 provides a signal of a high level, and transistor Q45 provides a signal of a low level.
According to the above-described flipflop circuit 102, data in the master circuit is applied when clock signal C0 attains a high level, and data in the slave circuit is updated when clock signal C0 attains a low level.
In flipflop circuit 102, bipolar transistors Q31 and Q32 having the emitter terminals connected to each other and bipolar transistors Q33 and Q36 having the emitter terminals connected to each other are connected in series between power supply terminals Vcc and Vee. A circuit having such a circuit configuration is called a two-stage series gate type circuit.
FIG. 18 is a circuit diagram showing a structure of a 2-input selector circuit 110. Referring to FIG. 18, 2-input selector circuit 110 includes a select signal input terminal S, first and second data signal input terminals D1, D2, a data signal output terminal Q, first and second reference potential terminals VB1, VB2, and first and second power supply terminals Vcc and Vee. A threshold potential of a logic amplitude of the signal entered to first and second data signal input terminals D1 and D2 is applied to first reference potential terminal VB1. A threshold potential of a logic amplitude of the signal entered to bipolar transistor Q50 is applied to second reference potential terminal VB2.
2-input selector circuit 110 includes a resistor R8, bipolar transistors Q47-Q54, and constant current sources CS18-CS20. Transistor Q47 has its base connected to select signal input terminal S, its collector connected to first power supply terminal Vcc, and its emitter connected to second power supply terminal Vee via constant current source CS18. Transistors Q48 and Q52 have their bases connected to first and second data signal input terminals D1 and D2, respectively, their collectors both connected to first power supply terminal Vcc, and their emitters connected to the collectors of transistors Q50 and Q53, respectively. Transistors Q42 and Q51 have their bases both connected to first reference potential terminal VB1, and their collectors both connected to first power supply terminal Vcc via resistors R8, and their emitters connected to the collectors of transistors Q50 and Q53, respectively. Transistors Q50 and Q53 have their bases connected to the emitter of transistor Q47 and second reference potential terminal VB2, respectively, and their commonly-connected emitters connected to second power supply terminal Vee via constant current source CS19. Transistors Q54 has its base connected to the collector of transistor Q49, its collector connected to first power supply terminal Vcc, and its emitter connected to data signal output terminal Q as well as to second power supply terminal Vee via constant current source CS20.
The operation of 2-input selector circuit 110 of FIG. 18 will be described. When the signal applied to select signal input terminal S attains a high level, bipolar transistor Q50 is turned on and bipolar transistor Q53 is turned off. When a signal of a high level is applied to data signal input terminal D1 under this state, transistor Q48 is turned on and transistor Q49 is turned off. As a result, the current of constant current source CS19 flows via transistors Q48 and Q50. Therefore, no current flows in resistor R8, and transistor Q54 provides a signal of a high level.
When the signal applied to select signal input terminal S attains a low level, transistor Q50 is turned off and transistor Q53 is turned on. If a signal of a high level is applied to data signal input terminal D2 under this state, transistor Q52 is turned on and transistor Q51 is turned off. As a result, the current of constant current source CS19 flows via transistors Q52 and Q53. Therefore, no current flows in resistor R8, and transistor Q54 provides a signal of a high level.
A similar operation is carried out when the signal applied to data input terminals D1 and D2 attains a low level. The data signal applied to data input terminal D1 and the data signal applied to data input terminal D2 are output via transistor Q54 when the select signal attains a high level and a low level, respectively.
In the above-described 2-input selector circuit 110, the signal applied to data signal input terminal D1 is output when the select signal attains a high level, and the signal applied to data signal input terminal D2 is output when the select signal attains a low level.
FIG. 19 is a circuit diagram showing a structure of a 3-input NOR gate 105. Referring to FIG. 19, 3-input NOR gate 105 includes data signal input terminals D0-D2, a data signal output terminal Q, a first reference potential terminal VB1, and first and second power supply terminals Vcc, Vee. A threshold potential of a logic amplitude of the signals applied to data terminals D0-D2 is provided to first reference potential terminal VB1.
3-input NOR gate 105 further includes bipolar transistors Q55-Q59, a resistor R9, and constant current sources CS21 and CS22. Transistors Q55-Q57 have their bases connected to data signal input terminals D2, D1, and D0, respectively, their commonly-connected collectors connected to first power supply terminal Vcc via resistor R9, and their commonly-connected emitters connected to second power supply terminal Vee via constant current source CS21. Transistor Q58 has its base connected to first reference potential terminal VB1, its collector connected to first power supply terminal Vcc, and its emitter connected to the emitters of transistors Q55-Q57. Transistor Q59 has its base connected to the collectors of transistors Q55-Q57, its collector connected to first power supply terminal Vcc, and its emitter connected to data signal output terminal Q as well as to second power supply terminal Vee via constant current source CS22.
The operation of 3-input NOR gate 105 of FIG. 19 will be described hereinafter. In this circuit, bipolar transistor Q58 is turned off when any of the signals applied to data signal input terminals D0-D2 attains a high level. Therefore, the current from constant current source CS21 flows to resistor R9 via any of transistors Q55-Q57 turned on, whereby data signal output terminal Q provides a signal of a low level.
Bipolar transistor Q58 is turned on when all the signals applied to data signal input terminals D0-D2 attain a low level. The current from constant current source CS21 flows through transistor Q58, and current will not flow in resistor R9. Therefore, data signal output terminal Q provides a signal of a high level. Thus, this gate forms a 3-input NOR logic.
In FIG. 14, a 4-bit counter circuit 101 is formed of flipflop circuits 102-104, and a 3-input NOR gate 105. In 4-bit counter circuit 101, each output Q of flipflop circuits 102 and 103 is sequentially applied to input D of a succeeding stage of flipflop circuits 103 and 104, so that data is shifted for every cycle of clock signal C0. Since 3-input NOR gate 105 receives output Q of each of three flipflop circuits 102-104, a signal of a high level is output for only 1 cycle for every 4 cycles of clock signal C0. By taking an inverted output QB of flipflop circuit 102 in the 4-bit counter, a select signal SEL is obtained that provides a low level for only 1 cycle for every 4 cycles of clock signal C0, as shown in FIG. 15(d). This signal is applied to select signal input terminal S of 2-input selector circuits 110-112.
Externally applied data signals I0-I2 are provided to each data signal input terminal D1 of selector circuits 112, 111, and 110. Externally applied data I3 is provided to data signal input terminal D of flipflop circuit 106. Each output Q of flipflop circuits 106-108 is connected to each data signal input terminal D2 of selector circuits 110-112. Selector circuits 110-112 output data of input terminal D2 and input terminal D1 when select signal SEL attains a low level and a high level, respectively. Thus, externally applied parallel data signals I0-I3 are captured by the flipflop circuit when select signal SEL attains a low level, and shifted and held by the flipflop circuit when the select signal SEL attains a high level. The parallel data signals are output from flipflop circuit 109 as a serial data signal Z as shown in FIG. 15(e).
FIG. 20 is a block diagram showing a structure of a conventional interleave type 1:4 demultiplexer circuit 110 described in pp. 35-38 in "Bipolar Circuits and Technology Meeting", IEEE 1991. FIG. 21 is a timing chart showing the operation thereof. Referring to FIG. 20, a demultiplexer circuit 110 includes a clock signal input terminal C', a data signal input terminal D', and data signal output terminals Q0'-Q3'. A clock signal CO is applied to clock signal input terminal C'. Clock signal C0 attains a high level or a low level for every half cycle Tc/2 as shown in FIG. 21(b). A serial data signal I is applied to data signal input terminal D'. Data signal I attains a high level or a low level at the same cycle of clock signal C0 in synchronization with a rise of clock signal C0, as shown in FIG. 21(a).
Demultiplexer circuit 110 includes flipflop circuits 112, 115-126, and latch circuits 113, 114.
Latch circuit 113 will first be described with reference to the structure of FIG. 22 and the timing chart of FIG. 23. Referring to FIG. 22, latch circuit 113 includes a clock signal input terminal C, a data signal input terminal D, data signal output terminals Q, QB, first and second reference potential terminals VB1, VB2, and first and second power supply terminals Vcc and Vee.
A clock signal C0 is applied to clock signal input terminal C. As shown in FIG. 23(c), clock signal C0 attains a low level and a high level for every half cycle Tc/2. Data signal I is applied to data signal input terminal D. As shown in FIG. 23(a), data signal I attains a high level and a low level at the same cycle of clock signal C0 in synchronization with a fall of clock signal C0.
A threshold potential having a logic amplitude of data signal I is applied to first reference potential terminal VB1. A threshold potential having a logic amplitude of clock signal C0 is applied to second reference potential terminal VB2.
Latch circuit 113 includes bipolar transistors Q60-Q67, resistors R10, R11, and constant current sources CS23-CS25. Transistors Q60 and Q61 have their bases connected to data signal input terminal D and first reference potential terminal VB1, their collectors connected to first power supply terminal Vcc via resistors R10 and R11, respectively, and their commonly-connected emitters connected to the collector of transistor Q62. Transistors Q63 and Q64 have their bases connected to the collectors of transistors Q61 and Q60, respectively, their collectors connected to the collectors of transistors Q60 and Q61, respectively, and their commonly-connected emitters connected to the collector of transistor Q65. Transistors Q62 and Q65 have their bases connected to second reference potential terminal VB2 and clock signal input terminal C, respectively, and their commonly-connected emitters connected to second power supply terminal Vee via constant current source CS23. Transistors Q66 and Q67 have their bases connected to the collectors of transistors Q61 and Q60, respectively, and their collectors both connected to first power supply terminal Vcc, and their emitters connected to data signal output terminals Q and QB, respectively, as well as to second power supply terminal Vee via constant current sources CS20 and CS25, respectively.
Latch circuit 13 has a circuit structure identical to that of the master circuit portion of flipflop circuit 102 of FIG. 16. Bipolar transistors Q60 and Q61 form a data writing circuit and bipolar transistors Q63 and Q64 form a data holding circuit.
The operation of latch circuit 113 of FIG. 22 will be described hereinafter. When clock signal C0 applied to clock signal input terminal C attains a high level, bipolar transistor Q62 is turned on, and the data writing circuit is turned on. Bipolar transistor Q65 is turned off, and the data holding circuit is turned off. If the data signal (assumed to be ID1) applied to transistor Q60 attains a high level under this state, transistor Q60 is turned on and transistor Q61 is turned off. The current from constant current source CS23 flows to resistor R10 via Q60 and Q62. As a result, transistor Q67 provides a signal of a low level. No current flows in resistor R11 since transistor Q61 is turned off. Therefore, transistor Q66 provides a signal of a high level.
When clock signal C0 applied to clock signal input terminal C is brought to a low level from a high level (time t1 in FIG. 23), bipolar transistor Q65 is turned on, and the data holding circuit is turned on. Bipolar transistor Q62 is turned off, and the data writing circuit is turned off. Bipolar transistors Q63 and Q64 have their base terminals and collector terminals cross-coupled to each other. Data signal ID1 applied during a high level of clock signal C0 causes transistor Q63 to be turned on and transistor Q64 to be turned off. Therefore, data signal ID1 is maintained. Transistors Q66 and Q67 continue to output the same value when clock signal C0 attains a high level.
As described above, latch circuit 113 enters data when clock signal C0 attains a high level, and maintains the data when clock signal C0 attains a low level.
In FIG. 20, flipflop circuit 112 and latch circuits 113 and 114 form an internal clock generation circuit 111. Since flipflop circuit 112 has inversion output QB connected to data input terminal D, the signal applied to clock output terminal C' is frequency-divided by a factor of 2 to be provided from data output terminal Q. Latch circuit 114 has inversion output QB connected to data input terminal D of latch circuit 113 according to a structure in which the operation of data entering and data holding is inverted by 180.degree. with respect to latch circuit 113. Therefore, latch circuits 113 and 114 further frequency-divide by a factor of 2 the output signal of flipflop circuit 112. Thus, internal clock generation circuit 114 has a function of a 1/4 frequency divider. By taking a complementary output of latch circuit 113 and a complementary output of latch circuit 114, 4 phases of overlap signals are obtained displaced in phase by 90.degree. from each other with 4 times the cycle of clock signal C0 applied to clock signal input terminal C' as shown in (c)-(f) in FIG. 21.
The 4 phases of overlap signals C(0.degree.)-C(270.degree.) become the clock signals of flipflop circuits 115-118 connected in parallel to data signal input terminal D'. Data I serially applied to data input terminal D' is entered into flipflop circuits 115-118 by four overlap signals C(0.degree.)-C(270.degree.) displaced in phase by 90.degree. from each other.
Flipflop circuits 119-122 are connected to the outputs of flipflop circuits 115-118, respectively. The data entered in flipflop circuits 115-118 are shifted and held according to the signal applied to clock input terminal C of flipflop circuits 119-122. Then, the data held in flipflop circuits 119-122 are entered into flipflop circuits 123-126 in synchronization with clock signal C(270.degree.) to be output in parallel.
In a conventional multiplexer circuit 100, only one select signal SEL generated by counter circuit 110 is used. The hardware was great since four flipflop circuits 106-109 and three selector circuits 110-112 are required for selecting and shifting data. This results in a great power consumption and a large layout area.
In a conventional demultiplexer circuit 110, a 1:4 demultiplexer circuit was formed using only four overlap signals C(0.degree.)-C(270.degree.) generated by internal clock generation circuit 111. The hardware was great since three flipflop circuits per bit was required for selecting and shifting serially input data. The power consumption and the layout area were great.